1. Technical Field
The present disclosure relates to an array substrate, a method of manufacturing the array substrate and a display apparatus having the array substrate. More particularly, the present invention relates to an array substrate of which electrical contact between wirings is repairable, a method of manufacturing the array substrate and a display apparatus having the array substrate.
2. Description of Related Art
Recently, a data driver IC and a gate driver IC (or scan driver IC) have been integrated on a liquid crystal display panel in order to reduce manufacturing cost and to meet market requirement of a narrow bezel. In order to acquire above integration, a scan driver circuit including amorphous silicon thin film transistor (a-Si TFT) needs a simple structure.
FIG. 1 is a diagram illustrating a conventional shift register. The shift register in FIG. 1, for example, may be used for a liquid crystal display apparatus.
Referring to FIG. 1, a scan driver circuit that generates a gate pulse for activating a scan line includes a shift register A unit stage of the shift register includes an S-R latch and an AND gate.
The S-R latch is activated based on a first input signal IN1 that corresponds to an output signal of a previous stage, and the S-R latch is inactivated based on a second input signal IN2 that corresponds to an output signal of a next stage. The AND gate generates a gate pulse (or scan signal) when the S-R latch is activated and clock is high.
In detail, first and second clocks CKV and CKVB applied to each unit stage for driving odd and even numbered scan lines have opposite phase to each other.
The shift register in FIG. 1 may be formed and have a structure shown as in following FIG. 2.
FIG. 2 is a circuit diagram illustrating a unit stage in FIG. 1.
Referring to FIGS. 1 and 2, a unit stage of a shift register includes a buffer section 10, a charging section 20, a driving section 30 and a discharging section 40. The unit stage outputs a gate signal (or scan signal) based on a scan start signal STY or an output signal of a previous stage.
In detail, the buffer section 10 includes a first transistor Q1 that has gate and drain electrodes electrically connected to each other and a source electrode electrically connected to a first node N1. A first input signal IN1 is applied to the gate and drain electrodes of the first transistor Q1.
The charging section 20 includes a capacitor C. A first end of the capacitor C is electrically connected to the first node N1. A second end of the capacitor C is electrically connected to the driving section 30.
The driving section 30 includes a second transistor Q2 and a third transistor Q3. The second transistor Q2 includes a drain electrode that is electrically connected to a clock terminal CK, a gate electrode that is electrically connected to the first node N1, and a source electrode that is electrically connected to the second end of the capacitor and an output terminal OUT. The third transistor Q3 includes a drain electrode that is electrically connected to the source electrode of the second transistor Q2 and the capacitor C, and a source electrode that is electrically connected to a first power voltage terminal VSS.
A first clock CKV or a second clock CKVB of which phase is opposite to the first clock CKV is applied to the clock terminal CK.
The discharging section 40 includes a fourth transistor Q4. The fourth transistor Q4 includes a drain electrode that is electrically connected to the first node N1, a gate electrode that is electrically connected to a gate electrode of the third transistor Q3, and a source electrode that is electrically connected to the first power voltage terminal VSS. A second input signal IN2 is applied to both of the gate terminals of the third and fourth transistors Q3 and Q4.
When the first input signal N1 is high, the capacitor C is electrically charged. When the second input signal IN2 is high, the capacitor C is electrically discharged. Therefore, S-R latch operation is performed.
When the capacitor C is electrically charged, the first or second clock CKV or CKVB that is applied to the clock terminal CK is outputted through the second transistor Q2 that is turned on. Therefore, all switching devices (or a-Si TFTs) that are electrically connected to the output terminal OUT are turned on. When the second input signal IN2 is high, the third transistor Q3 is turned on to pull down a voltage of the output terminal OUT to be equal to a first power voltage of the first power voltage terminal VSS.
Therefore, the first and second clocks CKV and CKVB, preferably, have a high voltage of about 15V in order to turn on the a-Si TFTs, and the first power voltage of the first power voltage terminal VSS preferably has a low voltage of about −7V in order to turn off the a-Si TFTs.
As described above, in order to output scan signal that activates the switching devices formed in a display region, the shift register requires the first clock CKV or the second clock CKVB, and a first power voltage that is applied to the first power voltage terminal VSS.
In order to apply the first or second clock CKV or CKVB and the first power voltage, a plurality of wirings and a plurality of contact regions that connect the wirings to the shift register are required. Additionally, in order to electrically connect transistors Q1, Q2, Q3 and Q4 and capacitor C of the shift register with one another, a plurality of contact regions is formed.
When one of the contact regions is electrically opened, no signal is applied to a scan line that corresponds to the contact region and scan lines disposed below the scan line that corresponds to the contact region to induce defects. Therefore, display quality is deteriorated.
Furthermore, a large current flows through the wirings. Therefore, when the contact region is unstable, the contact region is easily opened. In order to repair such an opening of the contact region, separate wirings for a repair are required.